CMOS Technology for Biomedical Oriented System-on-Chip Applications Seminar

CMOS Technology for Biomedical Oriented System-on-Chip Applications Seminar

In this paper a low-power small-area 1-bit CMOSbased adder cell is being introduced. It needs only 14 transistors and relies on low-power XOR/XNOR cells, transmission function logic and pass-gate logic cells to compute the sum and carry-out bits with rail-to-rail output swing. The proposed adder cell, which has been designed and laid out according to the layout requirements of a 0.35 μm 3.30 V CMOS technology, consumes 45% less power and occupies 47% less area than the 28-transistor standard cell provided by the technology supplier, making it attractive for being used in low-power applications, such as in a Biomedical-oriented system-on-chip design.

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